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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD46128953-X
128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
Description
The PD46128953-X is a high speed, low power, 134,217,728 bits (4,194,304 words by 32 bits) CMOS Mobile Specified RAM featuring synchronous burst read and synchronous burst write function. The PD46128953-X realizes high performance with the SDR interface, command and data inputs / outputs are synchronized the rising edge of clock. The PD46128953-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
* 4,194,304 words by 32 bits organization * Low voltage operation: 1.7 to 2.0 V (1.850.15 V) * Operating ambient temperature: TA = -25 to +85 C * Synchronous burst mode Burst length : 8 double words (Wrap) Burst sequence : Linear burst Maximum clock frequency : 83 / 66 MHz * SDR (Single Data Rate) Architecture One data transfers per one clock cycle All inputs/outputs are synchronized with the positive edge of the clock * Write data mask (DM) for write operation * Output Enable: /OE pin * Chip Enable input: /CE1 pin * Standby Mode input: CE2 pin * Standby Mode 1: Normal standby (Memory cell data hold valid) * Standby Mode 2: Density of memory cell data hold is variable
PD46128953
Clock frequency MHz (MAX.) -E12X -E15X
Note
Operating supply voltage V 1.7 to 2.0
Operating ambient temperature C -25 to +85 60 55
Supply current
At operating mA (MAX.)
At standby A (MAX.)
83 66
T.B.D.
Note Under consideration
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. M17506EJ1V1DS00 (1st edition) Date Published September 2005 CP (K) Printed in Japan
2005
PD46128953-X
Ordering Information
PD46128593-X is mainly shipping by wafer.
Please consult with our sales offices for package samples and ordering information.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Pin Configuration
The following is pin configuration of package sample. /xxx indicates active low signal. 127-pin PLASTIC FBGA (13.0 x 11.5)
Top View
14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDE FGH J K LMNP PNML K J HGF EDCB A
Bottom View
Top View
A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC NC NC NC NC NC NC NC NC NC NC B NC NC NC NC DQ28 DQ29 DQ30 DQ31 NC NC VSS NC DQ26 DQ27 NC NC /WE CLK DM0 NC NC NC DQ25 NC NC NC CE2 /ADV DM1 NC NC DM2 DQ24 NC NC NC NC /WAIT NC NC NC DM3 VDD NC NC NC NC NC NC NC NC VDD VSSQ NC NC DQ23 NC A/DQ15 DQ22 VSS A/DQ7 A/DQ21 NC C D E F G H J K L M N NC NC NC P NC NC NC
A/DQ20 A/DQ19 A/DQ14 A/DQ18 A/DQ5 NC A/DQ11 A/DQ2 A/DQ8 NC NC A/DQ17 A/DQ16 VDDQ VSSQ NC NC NC NC NC NC NC NC NC NC NC
A/DQ6 A/DQ13 A/DQ12 NC VDD A/DQ1 VSSQ NC VSS A/DQ4 A/DQ3 A/DQ9 /OE NC NC VDDQ VDDQ A/DQ10 A/DQ0 /CE1 NC
A/DQ0 to A/DQ021 : Address inputs , Data inputs/ outputs DQ22 to DQ31 /CE1 CE2 /WE /OE CLK /ADV : Data inputs / outputs : Chip select input : Standby mode input : Write enable input : Output enable input : Clock input : Address valid
/WAIT VDD VSS VDDQ VSSQ NC
Note
: Wait output : Power supply : Ground : Power supply for DQ : Ground for DQ : No Connection
DM0 to DM3 : Write data mask input
Note Some signals can be applied because this pin is not internally connected. Remark Refer to 10. Package Drawing for the index mark.
Preliminary Data Sheet M17506EJ1V1DS
3
PD46128953-X
Pin Function (1/2)
Symbol A/DQ0 to A/DQ21 Synchronous address input/data input/output These pins are used as address input pins and data input/output pins. When they are used as address input pins, the input address is latched at the rising edge of CLK. When the address is latched, the setup time and hold time must be satisfied at the rising edge of CLK. When they are used as data input/output pins, the input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output from these pins at the rising edge of CLK. DQ22 to DQ31 Synchronous data input/output. While the A/DQ pins function as address input pins and data input/output pins, these pins function only as data input/output pins. The input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output at the rising edge of CLK. CLK Input clock. Addresses and control signals are latched in synchronization with this signal. All the synchronous input signals must satisfy the setup time and hold time at the rising edge of CLK. /ADV Synchronous address valid input signal. An address is latched at the rising edge of CLK while /ADV is LOW. When the address is latched, the setup time and hold time must be satisfied at the rising edge of CLK. Note: This signal serves as an asynchronous signal when the mode register set or read. /CE1 Synchronous chip enable input. This device is active while /CE1 is LOW. When inputting /CE1, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register set or read. CE2 Asynchronous power-down mode input When this signal is made LOW, the device enters the power-down mode status. CE2 is not synchronized with the clock. It is an asynchronous signal. /OE Synchronous output enable input. When this signal is made LOW, read data is output. When inputting /OE, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register set or read. /WE Synchronous write enable input. When /WE inputs a LOW at the same time as /ADV, the device recognizes a write operation. When inputting /WE, the setup time and hold time must be satisfied at the rising edge of CLK. Remark This signal serves as an asynchronous signal when the mode register is set or read. Description
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
(2/2)
Symbol DM0 to DM3 Synchronous write data mask input. These signals can mask write data during burst write. To input data mask, the setup time and hold time must be satisfied at the rising edge of CLK. Data mask can be controlled in byte units. DM0: A/DQ0 to ADQ7 DM1: A/DQ8 to ADQ15 DM2: A/DQ16 to ADQ21, DQ22 to DQ23 DM3: DQ24 to DQ31 /WAIT Synchronous wait output. /WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready. The wait signal is output at the rising edge of CLK. VDD Supply voltage: Usually, the supply voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation Conditions. VSS VDDQ Supply voltage: Ground Supply voltage: Supply voltage for DQ. Usually, this voltage is 1.85 V. Refer to DC Characteristics and Recommended Operation Conditions. VSSQ NC Supply voltage: Ground for DQ. No connection Some signals can be applied because this pin is not internally connected. Description
Preliminary Data Sheet M17506EJ1V1DS
5
PD46128953-X
Block Diagram
VDD Standby mode control VSS VDDQ VSSQ Refresh control Refresh state control
Refresh counter Row decoder Address buffer Memory cell array 134,217,728 bits
/ADV
Address latch Sense amplifier / Switching circuit Column decoder
/CE1 /WAIT CE2 /WE Command control Burst counter
Data control
Latch circuit
CLK
Clock control
Input / Output buffer
DM0 to DM3 /OE
A/DQ0 to A/DQ21 DQ22 to DQ31
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Truth Table
Mode Deselect (Standby Mode 1) Power Down (Standby Mode 2) Output Disable Start Address Latch
Note2 Note3 Note1
/CE1 H x L
CE2 H L H
CLK
/ADV x
/OE x x H H x H H x x
/WE x x x x x H L x x
A/DQ0-A/DQ21 , DQ22-DQ31 High-Z High-Z High-Z High-Z Low-Z or High-Z High-Z High-Z Low-Z to High-Z High-Z
x
x x L H L L
Start Address not Latch Read Command input Write Command input
Note2 Note2 Note4 Note4
Burst Read Termination Burst Write Termination
L to H
x x
Notes 1. 2. 3. 4. Remark
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition). Start address latch and read/write command input are performed at the next rising edge of clock when /ADV is transferred HIGH to LOW. It is impossible that Start address latch and read/write command input are performed at the first rising edge of clock during /ADV is fixed HIGH. Refer to 3.6 Burst Read Termination, 3.7 Burst Write Termination. H, HIGH: VIH, L, LOW: VIL, x: VIH or VIL For read/write operation, refer to 7 Timing Charts.
Preliminary Data Sheet M17506EJ1V1DS
7
PD46128953-X
CONTENTS
1. Initialization ................................................................................................................................................ 10 2. Partial Refresh ........................................................................................................................................... 11
2. 1 Standby Mode......................................................................................................................................................... 11 2. 2 Density Switching ................................................................................................................................................... 11 2. 3 Standby Mode Status Transition............................................................................................................................. 11 2. 4 Addresses for Which Partial Refresh Is Supported................................................................................................. 12
3. Burst Operation ......................................................................................................................................... 13
3. 1 Features of Burst Operation ................................................................................................................................... 13 3. 2 Latency ................................................................................................................................................................... 13 3. 3 Burst Length, Burst Sequence, Wrap Around ......................................................................................................... 16 3. 4 Burst Read End ...................................................................................................................................................... 17 3. 5 Burst Write End ...................................................................................................................................................... 18 3. 6 Burst Read Termination.......................................................................................................................................... 19 3. 7 Burst Write Termination .......................................................................................................................................... 20 3. 8 /WAIT signal behavior............................................................................................................................................. 21 3. 9 /WAIT output........................................................................................................................................................... 21
4. Mode Register Settings............................................................................................................................. 23
4. 1 Mode Register Setting Method ............................................................................................................................... 23 4. 1. 1 Cautions for Setting Mode Register............................................................................................................. 23 4. 1. 2 Mode Register Setting/Reading................................................................................................................... 25 4. 1. 3 Partial refresh Density ................................................................................................................................. 25 4. 1. 4 Burst length ................................................................................................................................................. 25 4. 1. 5 Function mode............................................................................................................................................. 26 4. 1. 6 Driver strength ............................................................................................................................................. 26 4. 1. 7 Read Latency .............................................................................................................................................. 26 4. 1. 8 Single Write ................................................................................................................................................. 26 4. 1. 9 Valid Clock Edge ......................................................................................................................................... 26 4. 1. 10 Reset to Asynchronous.............................................................................................................................. 26 4. 1. 11 /WE control................................................................................................................................................ 26 4. 1. 12 Setting of unused bits ................................................................................................................................ 26 4. 2 Mode Register Reading .......................................................................................................................................... 27 4. 2. 1 Cautions for Setting Mode Register............................................................................................................. 27 4. 2. 2 Data read from mode register...................................................................................................................... 27
5. Address, /OE, /WE, DM control ................................................................................................................ 29
5. 1 Relation of address inputs and /OE control ............................................................................................................ 29 5. 2 Address Latching .................................................................................................................................................... 30 5. 3 Read / Write Command Loading............................................................................................................................. 32 5. 4 /OE control during burst read operation.................................................................................................................. 34 5. 4. 1 /OE HIGH to LOW during burst read operation ........................................................................................... 34 5. 4. 2 /OE LOW to HIGH during burst read operation ........................................................................................... 35 5. 5 Write data mask signal (DM) control....................................................................................................................... 36 5. 5. 1 Controlling write data mask signal (DM) in write cycle ................................................................................. 36 5. 5. 2 Write data mask (DM) truth table................................................................................................................. 37 8
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
6. Electrical Specifications ........................................................................................................................... 38 7. Timing Charts............................................................................................................................................. 43 8. Mode Register Setting/Read Timing........................................................................................................ 49
8. 1 Mode Register Setting Timing ................................................................................................................................ 49 8. 2 Mode Register Setting Flow Chart .......................................................................................................................... 50 8. 3 Mode Register Read Timing ................................................................................................................................... 51 8. 4 Mode Register Read Flow Chart............................................................................................................................. 52
9. Standby Mode Timing Charts................................................................................................................... 53 10. Package Drawing..................................................................................................................................... 54 11. Recommended Soldering Conditions ................................................................................................... 55
Preliminary Data Sheet M17506EJ1V1DS
9
PD46128953-X
1. Initialization
Initialize the PD46128953-X at power application using the following sequence to stabilize internal circuits. (1) Following power application, make CE2 HIGH after fixing CE2 to LOW for the period of tVHMH. Make /CE1 HIGH before making CE2 HIGH. (2) /CE1 and CE2 are fixed HIGH for the period of tMHCL. Normal operation is possible after the completion of initialization. Figure 1-1. Initialization Timing Chart
Initialization Normal Operation
/CE1 (Input) tCHMH tVHMH CE2 (Input) tMHCL
VDD
VDD (MIN.)
Cautions 1. 2.
Make CE2 LOW when starting the power supply. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VDD (MIN.)).
Initialization Timing
Parameter Power application to CE2 LOW hold /CE1 HIGH to CE2 HIGH Following power application CE2 HIGH hold to /CE1 LOW Symbol tVHMH tCHMH tMHCL MIN. 50 0 300 MAX. Unit
s
ns
s
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
2. Partial Refresh
2. 1 Standby Mode In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs partial refresh, is also provided. 2. 2 Density Switching In Standby Mode 2, the densities that can be selected for performing refresh are 64M bits, 32M bits, 16M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (For how to perform mode register settings, refer to section 4. Mode Register Settings.) 2. 3 Standby Mode Status Transition In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 64M bits, 32M bits, or 16M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2. For the timing charts, refer to Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit Timing Chart, Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M17506EJ1V1DS
11
PD46128953-X
Figure 2-1. Standby Mode State Machine
Power On
Initialization
Mode Register Setting CE2 = VIH /CE1 = VIL
Active CE2 = VIL
/CE1 = VIH, CE2 = VIH
CE2 = VIL
/CE1 = VIL, CE2 = VIH
/CE1 = VIL, CE2 = VIH
Standby Mode 1
CE2 = VIL
Standby Mode 2 (64M bits / 32M bits / 16M bits)
CE2 = VIL Standby Mode 2 (Data not held)
2. 4 Addresses for Which Partial Refresh Is Supported
Data hold density 64M bits 32M bits 16M bits Correspondence address 000000H to 1FFFFFH 000000H to 0FFFFFH 000000H to 07FFFFH
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
3. Burst Operation
3. 1 Features of Burst Operation
Function Burst Length Burst Wrap Burst Sequence Valid Clock Edge Latency Count Read Latency Write Latency 8 double words Wrap Linear CLK Rising Edge 6, 7, 8 5, 6, 7 Features
3. 2 Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through Mode Register Set sequence after power-up. Once RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. Latency Count
Grade -E12X -E15X Clock Frequency <83 MHz <66 MHz Read Latency 7, 8 6, 7, 8 Write Latency 6, 7 5, 6, 7
Note
Note Write Latency = Read Latency-1
Preliminary Data Sheet M17506EJ1V1DS
13
PD46128953-X
Figure 3-1. Latency Configuration (Read)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK (Input)
/ADV (Input)
/CE1 (Input) Read Latency = 6 A/DQ0 to A/DQ21 (Input/Output) DQ22 to DQ31 (Output) High-Z Add Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
High-Z Read Latency = 7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A/DQ0 to A/DQ21 (Input/Output)
High-Z
Add
Q0
Q1
Q2
Q3
Q4
Q5
Q6
DQ22 to DQ31 (Output)
High-Z Read Latency = 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
A/DQ0 to A/DQ21 (Input/Output)
High-Z
Add
Q0
Q1
Q2
Q3
Q4
Q5
DQ22 to DQ31 (Output)
High-Z
Q0
Q1
Q2
Q3
Q4
Q5
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Figure 3-2. Latency Configuration (Write)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK (Input)
/ADV (Input)
/CE1 (Input)
Write Latency = 5 A/DQ0 to A/DQ21 (Input) High-Z Add D0 D1 D2 D3 D4 D5 D6 D7
DQ22 to DQ31 (Input)
High-Z Write Latency = 6
D0
D1
D2
D3
D4
D5
D6
D7
A/DQ0 to A/DQ21 (Input)
High-Z
Add
D0
D1
D2
D3
D4
D5
D6
D7
DQ22 to DQ31 (Input)
High-Z Write Latency = 7
D0
D1
D2
D3
D4
D5
D6
D7
A/DQ0 to A/DQ21 (Input)
High-Z
Add
D0
D1
D2
D3
D4
D5
D6
DQ22 to DQ31 (Input)
High-Z
D0
D1
D2
D3
D4
D5
D6
Preliminary Data Sheet M17506EJ1V1DS
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PD46128953-X
3. 3 Burst Length, Burst Sequence, Wrap Around The burst length is 8 double words and the corresponding address is (A/DQ2, A/DQ1, A/DQ0). A burst operation that extends over addresses higher than A/DQ3 cannot be executed. Wrap-around is performed within the burst length of 8 double words. Refer to Table 3-1. Burst Sequence. Table 3-1. Burst Sequence
Start Address (A/DQ2 , A/DQ1, A/DQ0) Burst Sequence Linear , Wrap 1st data - 2nd data - 3rd data - 4th data - 5th data - 6th data - 7th data - 8th data (0, 0, 0) (0, 0, 1) (0, 1, 0) (0, 1, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0) (1, 1, 1) (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) (1, 0, 0) - (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) (1, 0, 1) - (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) (1, 1, 0) - (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) (1, 1, 1) - (0, 0, 0) - (0, 0, 1) - (0, 1, 0) - (0, 1, 1) - (1, 0, 0) - (1, 0, 1) - (1, 1, 0)
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
3. 4 Burst Read End The memory output goes into a high impedance state after completion of the burst read operation of the eighth double word. Therefore, no data is output from the memory even if CLK is kept input while /CE1 = LOW after the burst read operation of 8 words has been completed. Figure 3-3. Burst Read End
T9 CLK (Input) T10 T11 T12 T13 T14 T15
/ADV (Input)
H
/CE1 (Input)
L
/OE (Input)
L tAC tHZ Q7 High-Z
A/DQ0 to A/DQ21 (Output)
Q5
Q6
DQ22 to DQ31 (Output)
Q5
Q6
Q7
High-Z
Remark Memory output goes into a high impedance state after the last data (Q7) read by the burst operation has been output.
Preliminary Data Sheet M17506EJ1V1DS
17
PD46128953-X
3. 5 Burst Write End The memory does not input write data to internal circuits even if CLK is kept input with /CE1 = LOW and write data is input from the controller after completion of a burst write operation of 8 double words. Figure 3-4. Burst Write End
T8 T9 T10 T11 T12 T13 T14
CLK (Inout)
/ADV (Input)
H
/CE1 (Input)
L
/WE (Input)
tWDS tWDH A/DQ0 to A/DQ21 (Input) D5 D6 D7 A B C High-Z
DQ22 to DQ31 (Input)
D5
D6
D7
A
B
C
High-Z
Remark The memory does not input any write data to internal circuits even if write data (A, B, or C) is input after the last burst write data (D7) has been input, as shown in Figure 3-4.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
3. 6 Burst Read Termination A burst read termination is executed when /CE1 is made HIGH during a burst read operation. The command that the burst read termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the read data is output before the command of the burst read termination (/CE1 = HIGH) is input. Figure 3-5. Burst Read Termination
T4 CLK (Input) T5 T6 T7 T8 T9 T10
/ADV (Input)
H tCEH tCES
/CE1 (Input)
/OE (Input)
L tAC tHZ Q4 High-Z
A/DQ0-A/DQ21 (Output)
Q0
Q1
Q2
Q3
DQ22-DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
High-Z
Remark If the burst read termination is performed (/CE1: LOW HIGH) before the rising edge of CLK in T8, as shown in Figure 3-5, determined data is output as the read data (Q4) from the rising edge of CLK in T7. The burst read termination is valid after the initial read data has been output. (For the burst read termination, refer to Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 control).)
Preliminary Data Sheet M17506EJ1V1DS
19
PD46128953-X
3. 7 Burst Write Termination A burst write termination is executed when /CE1 is made HIGH during a burst write operation. The command that the burst write termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the write data is written before the command of the burst write termination (/CE1 = HIGH) is input. Figure 3-6. Burst Write Termination
T3 T4 T5 T6 T7 T8 T9
CLK (Input)
/ADV (Input)
H
tCEH tCES /CE1 (Input)
/WE (Input)
tWDS tWDH A/DQ0 to A/DQ21 (Input) D0 D1 D2 D3 D4 D5 High-Z
DQ22 to DQ31 (Input)
D0
D1
D2
D3
D4
D5
High-Z
Remark If the burst write termination is performed (/CE1: LOW HIGH) before the rising edge of CLK in T8, as shown in Figure 3-6, the write data is input to memory at the rising edge of CLK in T7. The write data input in cycle T8 (D5) is invalid. The burst termination is valid after the initial write data has been input. (For the burst write termination refer to Figure 7-6. Burst Write Termination Cycle Timing Chart (/CE1 control).)
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
3. 8 /WAIT signal behavior /WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready. The wait signal is output at the rising edge of CLK. Table 3-2. Relation Between Internal Operation of Memory and /WAIT Output
Internal Operation of Memory Preparation for burst read/burst write in progress Completion of preparation for burst read/burst write LOW HIGH /WAIT output
3. 9 /WAIT output The /WAIT output is enabled after specified time from CLK. /WAIT output is transferred LOW to HIGH one cycle before 1st burst read data output and 1st burst write data input. Figure 3-7. /WAIT Output Timing (Read Cycle)
T0 T1 T2 T3 T4 T5 T6
CLK (Input)
/ADV (Input) Read Latency = 6 A/DQ0 to A/DQ21 (Input/Output) High-Z Add Q0
DQ22 to DQ31 (Output)
High-Z tCEWA
Q0 tCLWA
1 cycle before latency cycle
/WAIT (Output)
Preliminary Data Sheet M17506EJ1V1DS
21
PD46128953-X
Figure 3-8. /WAIT Output Timing (Write Cycle)
T0 T1 T2 T3 T4 T5 T6
CLK (Input)
/ADV (Input) Write Latency = 5 A/DQ0 to A/DQ21 (Input) High-Z Add D0 D1
DQ22 to DQ31 (Input)
High-Z tCEWA tCLWA
D0
D1
1 cycle before latency cycle
/WAIT (Output)
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
4. Mode Register Settings
The default value of the mode register of the PD46128953-X is undefined upon power application. Therefore, be sure to set the mode register after power application and initialization. 4. 1 Mode Register Setting Method Each mode can be set by performing a total of six cycles of operations in succession after reading the most significant address (3FFFFFH) - two consecutive cycles for writing any data and three consecutive cycles for writing specific data (codes 1 to 3) - by an asynchronous access (with CLK fixed HIGH or LOW). Table 4-1. Mode Register Settings
Cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle Operation Read Write Write Write Write Write Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Don't care Don't care Don't care Code 1 (A/DQ0 = 1) Code 2 Code 3 Data
Codes 1 to 3 are set at the register. The register has a function to latch an address and data necessary for instruction execution, and does not occupy the memory. Whether the mode register is set or read can be selected by code 1 in the 4th bus cycle. If setting of the mode register is selected (A/DQ0 = 1) by code 1 in the 4th bus cycle, the contents of the mode register are set by code 2 in the 5th bus cycle and code 3 in the 6th bus cycle. The command contents are shown in Table 4-2. Mode Register Code 1 Definition (4th cycle), Table 4-3. Mode Register Code 2 Definition (5th cycle), and Table 4-4. Mode Register Code 3 Definition (6th cycle). For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart and Figure 8-2. Mode Register Setting Flowchart. If reading the mode register is selected by code 1 in the 4th bus cycle (A/DQ = 0), the contents of the mode register currently set in the 5th and 6th bus cycles can be read. If the mode register is read before it is set, any (undefined) data is read. For the mode register, refer to 4.2 Mode Register Reading. 4. 1. 1 Cautions for Setting Mode Register When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE. When setting a mod entry, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle and five write cycles). In the 1st bus cycle (read cycle), perform a toggle operation of /OE in the same manner as /CE1. If an illegal address or data is written or if an address and data are written in an incorrect sequence, the mode register is not correctly set. If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be stopped after the 4th bus cycle. If the normal sequence is executed up to the 5th bus cycle, setting of the mode register cannot be stopped until the 6th bus cycle is completed.
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PD46128953-X
Once the mode register has been set, the setting is retained while power is supplied and CE2 = HIGH, until it is re-set. If data is not retained by turning off the power or making CE2 LOW (except partial), however, the setting of the mode register is undefined. Re-set the register after power application or when returning from a data non-retention status. For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart and Figure 8-2. Mode Register Setting Flowchart. Table 4-2. Mode Register Code1 Definition (4th Bus Cycle)
Data Code A/DQ0 Symbol RW Function Mode Register Setting / Mode Register Reading A/DQ21 to A/DQ1 DQ31 to DQ22 - - - - Value 0 1 All "1" All "1" Description Mode Register Reading Mode Register Setting Reserved Reserved
Table 4-3. Mode Register Code2 Definition (5th Bus Cycle)
Data Code A/DQ1 to A/DQ0 Symbol PR Function Partial Refresh Density Value 00 01 10 11 A/DQ4 to A/DQ2 BL Burst length 000 001 010 011 100 101 110 111 A/DQ5 M Function Mode 0 1 A/DQ7 to A/DQ6 DS Driver Strength 00 01 10 11 A/DQ21 to A/DQ8 DQ31 to DQ22 - - - - All "1" All "1" 32M 16M 64M 0M Reserved Reserved 8 double words Reserved Reserved Reserved Reserved Reserved Synchronous Burst Reserved Strong Reserved Weak Middle Reserved Reserved Description
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Table 4-4. Mode Register Code3 Definition (6th Bus Cycle)
Data Code A/DQ2 to A/DQ0 Symbol RL Read Latency Function Value 000 001 010 011 100 101 110 111 A/DQ3 A/DQ4 N/A SW N/A Single Write 1 0 1 A/DQ5 VE Valid Clock Edge 0 1 A/DQ6 A/DQ7 RP WC Reset to Asynchronous /WE Control 1 0 1 A/DQ21 to A/DQ8 DQ31 to DQ22 - - - - 1 1 Reserved Reserved Reserved Reserved 6 7 8 Reserved Reserved Burst Read & Burst Write Reserved Reserved Rising Edge Reserved /WE Pulse Control Reserved Reserved Reserved Description
4. 1. 2 Mode Register Setting/Reading Select whether to set the mode register or read the set contents of the register by this item. If 1 is input to A/DQ0 in the 4th cycle, the mode register setting mode is set. If 0 is input to A/DQ0 in the 4th cycle, the mode register reading mode is set. For how to read the mode register, refer to 4.2 Mode Register Reading. 4. 1. 3 Partial refresh Density The partial refresh area is set by this item. If 00 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 32M bits are retained. If 01 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 16M bits are retained. If 10 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 64M bits are retained. If 11 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that all bits are not retained. 4. 1. 4 Burst length The burst length is set by this item. If 010 are input to A/DQ4, A/DQ3, and A/DQ2 in the 5th cycle, the burst length is set to 8. This product supports only a burst length of 8.
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PD46128953-X
4. 1. 5 Function mode The burst read mode is set by this item. If 0 is input to A/DQ5 in the 5th cycle, the burst mode is set. Be sure to input 0 to A/DQ5. 4. 1. 6 Driver strength The output driver strength is set by this item. If 00 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Strong. If 11 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Middle. If 10 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Weak. 4. 1. 7 Read Latency The read latency count is set by this item. If 100 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 6. If 101 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 7. If 110 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 8. Write latency is automatically set RL-1. 4. 1. 8 Single Write The write mode is set by this item, if 0 is input to A/DQ4 in the 6th cycle, the write mode is set to burst write. Be sure to input 0 to A/DQ4. 4. 1. 9 Valid Clock Edge The valid clock edge (Rising edge or Falling edge) is set in the burst mode. If 1 is input to A/DQ5 in the 6th cycle, rising edge is set to valid clock edge. 4. 1. 10 Reset to Asynchronous This function is not available now and reserved for future function. Be sure to input 1 to A/DQ6. 4. 1. 11 /WE control The input timing of /WE is set by this item. If 0 is input to A/DQ7 in the 6th cycle, the input timing of /WE is set to be the same as the timing of loading an address (/WE = LOW while /ADV = LOW). Refer to 5.3 Loading Command (read/write). Be sure to input 0 to A/DQ7. 4. 1. 12 Setting of unused bits Some of the undefined bits are used to enter a test mode that is not disclosed. Therefore, be sure to input 1 to the undefined bits (A/DQ21 to A/DQ1 and DQ31 to DQ22 in the 4th cycle, A/DQ21 to A/DQ8 and DQ31 to DQ22 in the 5th cycle, and A/DQ3, A/DQ21 to A/DQ8, and DQ31 to DQ22 in the 6th cycle).
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Preliminary Data Sheet M17506EJ1V1DS
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4. 2 Mode Register Reading If 0 is set to A/DQ0 in the 4th cycle after reading the most significant address (3FFFFFH) - two consecutive cycles for writing any data, it is possible to read current setting value of code 2 in the 5th cycle and current setting value of code 3 in the 6th cycle Table 4-5. Mode Register Settings
Cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle Operation Read Write Write Write Read Read Address 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH 3FFFFFH Don't care Don't care Don't care Code 1 (A/DQ0 = 0) Code 2 Code 3 Data
Codes 1 to 3 are written to the register. The register has a function to latch an address and data necessary for instruction execution, and does not occupy the memory. For the timing chart and flowchart, refer to Figure 8-3. Mode Register Read Timing Chart and Figure 8-4. Mode Register Read Flowchart. 4. 2. 1 Cautions for Setting Mode Register When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE. When setting the mode register, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle, three write cycles, and two mode register read cycles). In the 1st bus cycle (read cycle) and 5th and 6th bus cycles, perform a toggle operation of /OE in the same manner as /CE1. If an illegal address or data is written or if the codes are written in an incorrect sequence, reading the mode register fails and the mode register is not read correctly. If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be stopped after the 4th bus cycle. If the normal sequence is executed up to the 3rd bus cycle, setting of the mode register cannot be stopped until the 6th bus cycle is completed. 4. 2. 2 Data read from mode register If reading the mode register is started, the contents of currently set code 2 (partial refresh density, burst length, function mode, and driver strength) can be read in the 5th bus cycle. In the 6th bus cycle, the contents of currently set code 3 (read latency, single write, valid clock edge, reset to asynchronous, and /WE control) can be read. If the mode register is read before it is set, any (undefined) data is output. Set or read the mode register in compliance with the AC specifications in Table 4-6.
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PD46128953-X
Table 4-6. AC Specification of Mode Register Setting / Reading
Item Symbol -E12X, -E15X MIN. Specification of Mode Register Setting / Reading Cycle time Address setup time to /ADV = HIGH Address hold time to /ADV = HIGH /CE1 setup time to /ADV = HIGH Address setup time to /OE = LOW /ADV Low pulse width /OE to output in low impedance /OE to output valid /CE1 to output in high impedance /OE to output in high impedance Write data setup time to /WE = HIGH Write data hold time to /WE = HIGH /CE1 HIGH pulse width /WE LOW pulse width /OE LOW pulse width tMSC tAS tAH tCS tAOSM tVPL tOLZM tACM tCHZM tOHZM tDW tDH tCP tWP tOVL 20 0 10 50 50 90 6 1 6 0 6 5 30 10 10 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAX. Unit
For the timing chart and flowchart, refer to Figure 8-1. Mode Register Setting Timing Chart, Figure 8-2. Mode Register Setting Flowchart, Figure 8-3. Mode Register Read Timing Chart and Figure 8-4. Mode Register Read Flowchart.
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Preliminary Data Sheet M17506EJ1V1DS
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5. Address, /OE, /WE, DM control
5. 1 Relation of address inputs and /OE control This product uses only one pin to input an address and input/output DQ. Consequently, a bus fight may occur between an address input from the controller and data output from the memory and, therefore, the timing must be considered. Data is output after specified tOLZ from the first rising edge of CLK when /OE has changes its level from HIGH to LOW. Therefore, complete inputting an address from the controller before the first rising edge of CLK when /OE has changed its level from HIGH to LOW. Figure 5-1. Address inputs and /OE Timing
T0 CLK (Input) T1 T2 T3 T4 T5 T6 T7 T8
/ADV (Input)
tAH
/CE1 (Input)
tOEH tOES /OE (Input) tACH tAOS High-Z
tOLZ
A/DQ0 to A/DQ21 (Input/Output)
Add
Q0
Q1
Q2
Read Latency = 6 High-Z
DQ22 to DQ31 (Output)
Q0
Q1
Q2
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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PD46128953-X
5. 2 Address Latching An address is latched at the first rising edge of CLK when /ADV changes its level from HIGH to LOW while /CE1 = LOW. An address can be latched and a read or write operation can be started as soon as the memory has changed its status from standby (/CE1 = HIGH) to active (/CE1 = LOW). If the period in which /ADV = LOW while /CE1 = LOW extends over two or more CLK as shown in Figure 5-4, an address is latched at the first rising edge of CLK after /ADV = LOW. Figure 5-2. Address Latched Timing 1
T0 CLK (Input) T1 T2
tCHV tCSV tCHV /ADV (Input) tCES /CE1 (Input) tACS A/DQ0 to A/DQ21 (Input) Add tACH
tAH
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Figure 5-3. Address Latched Timing 2
T0 CLK (Input) T1 T2
tCHV tCSV tCHV /ADV (Input) tAH tCES /CE1 (Input) tACS A/DQ0 to A/DQ21 (Input) Add tACH
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification. Figure 5-4. Address Latched Timing 3
T0 T1 T2
CLK (Input) tCHV tCSV /ADV (Input) tAH tCES /CE1 (Input) tACS A/DQ0 to A/DQ21 (Input) tACH Add tCHV
Address Latched
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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PD46128953-X
5. 3 Read / Write Command Loading A command (read/write) is loaded in the same timing as an address (refer to 6.2 Address Latching). If /WE = HIGH at that time, a read operation is started; if /WE = LOW, a write operation is started. Figure 5-5 shows a read operation and Figure 5-6 shows a write operation. If /WE = LOW in the cycle next to that in which an address is loaded as shown in Figure 5-7, a write operation is not recognized. The operation in Figure 5-7 is a read operation. Figure 5-5. Command Loading Timing 1
T0 T1 T2
CLK (Input) tCHV tCSV tCHV /ADV (Input) tCES /CE1 (Input)
/OE (Input)
H tWES tWEH
/WE (Input)
Command Input
Remarks 1. 2.
Figure 5-5 shows a read operation Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Figure 5-6. Command Loading Timing 2
T0 T1 T2
CLK (Input) tCHV tCSV tCHV /ADV (Input) tCES /CE1 (Input)
/OE (Input)
H tWES tWEH
/WE (Input)
Command Input
Remarks 1. 2.
Figure 5-6 shows a write operation Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification. Figure 5-7. Command Loading Timing 3
T0 T1 T2
CLK (Input) tCHV tCSV /ADV (Input) tCES /CE1 (Input) tCHV
/OE (Input)
H tWES tWEH tWES tWEH
/WE (Input)
Command Input
Remarks 1. 2.
Figure 5-7 shows a read operation Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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PD46128953-X
5. 4 /OE control during burst read operation 5. 4. 1 /OE HIGH to LOW during burst read operation The output is controlled depending on the status of /OE (HIGH or LOW) when CLK rises. As shown in Figure 5-8, if /OE is made from LOW to HIGH before the rising edge of CLK in T8 during burst read, the read data (Q4) output from the rising edge of CLK in T7 is output. However, the read data that is output from the rising edge of CLK in T8 is not output. Figure 5-8. /OE HIGH to LOW during burst read operation Timing
T4 CLK (Input) T5 T6 T7 T8 T9 T10
/ADV (Input)
H
/CE1 (Input)
L
tOEH tOES /OE (Input) tAC tOH A/DQ0 to A/DQ21 (Output) Q0 Q1 Q2 Q3
tHZ Q4 High-Z
DQ22 to DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
High-Z
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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Preliminary Data Sheet M17506EJ1V1DS
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5. 4. 2 /OE LOW to HIGH during burst read operation The output is controlled depending on the status of /OE (HIGH or LOW) when CLK rises. As shown in Figure 5-9, if /OE is made from HIGH to LOW before the rising edge of CLK in T8 during burst read, the read data (Q5) output from the rising edge of CLK in T8 is output. Because /OE = HIGH until cycle T7, the read data (Q0, Q1, Q2, Q3, and Q4) that should be output when /OE = LOW are not output, but go into a high impedance state. Figure 5-9. /OE LOW to HIGH during burst read operation Timing
T4 T5 T6 T7 T8 T9 T10
CLK (Input)
/ADV (Input)
H
/CE1 (Input)
L
tOEH tOES /OE (Input) tOAC High-Z A/DQ0 to A/DQ21 (Output) Q0 Q1 Q2 Q3 tOLZ Q4 Q5 Q6 Q7
High-Z DQ22 to DQ31 (Output) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification.
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PD46128953-X
5. 5 Write data mask signal (DM) control This section explains how to control the write data mask signal (DM). DM is a signal that masks input data. Data mask is valid only in the write cycle. Therefore, data can be masked in the burst write cycle but cannot in the burst read cycle. The write data mask signal (DM) controls byte unit with one pin. - DM0 controls A/DQ7 to A/DQ0. - DM1 controls A/DQ15 to A/DQ8. - DM2 controls A/DQ21 to A/DQ16 and DQ23 to DQ22. - DM3 controls DQ31 to DQ24. 5. 5. 1 Controlling write data mask signal (DM) in write cycle As shown in Figure 5-10, the corresponding write data is masked when the write data mask signal (DM) is HIGH. Figure 5-10. Command Loading Timing 1
T0 T1 T2 T3 T4 T5 T6 T7
CLK (Input)
/ADV (Inout)
/WE (Input) tBDH tBDS tBDH tBDS DM (Input)
A/DQ0 to A/DQ21 (Input)
High-Z
Add
D0
Mask
D2
Mask
D4
DQ22 to DQ31 (Input)
High-Z
D0
Mask
D2
Mask
D4
Remark Refer to 6. Electrical Specifications, 7. Timing Charts in detail of AC specification
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Preliminary Data Sheet M17506EJ1V1DS
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5. 5. 2 Write data mask (DM) truth table Table 5-1. Write data mask (DM) truth table
Function DM0 All A/DQ and DQ write permission All A/DQ and DQ write prohibition A/DQ7 to A/DQ0 write permission A/DQ15 to A/DQ8 write permission DQ23 to DQ22, A/DQ21 to A/DQ16 write permission DQ31 to DQ24 write permission A/DQ7 to A/DQ0 write prohibition A/DQ15 to A/DQ8 write prohibition DQ23 to DQ22, A/DQ21 to A/DQ16 write prohibition DQ31 to DQ24 write prohibition L x x x H x x x x L x x x H x x DM1 L H x x L x x x H x x x x L x x x H DM DM2 DM3
Remark
H: VIH, L: VIL, x: VIH or VIL
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PD46128953-X
6. Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input / Output Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VDD VDDQ VT TA Tstg Condition -0.5 -0.5 -0.5 Rating
Note Note Note
Unit V V V C C
to +2.5 to +2.5 to +2.5
-25 to +85 -55 to +125
Note -1.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Supply voltage Input / Output Supply voltage Input HIGH voltage Input LOW voltage Operating ambient temperature Symbol VDD
Note1 Note1
Condition
MIN. 1.7 1.7 0.8VDDQ -0.3
Note2
MAX. 2.0 2.0 VDDQ +0.3 0.2VDDQ +85
Unit V V V V C
VDDQ VIH VIL TA
-25
Notes 1. 2.
Use same voltage condition (VDD = VDDQ). -0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Input / Output capacitance Symbol CIN COUT CDQ Test condition VIN = 0 V, Input pins VOUT = 0 V, /WAIT pin VDQ = 0 V, A/DQ, DQ pins MIN. TYP. MAX. 8 8 10 Unit pF pF pF
Remarks 1. 2.
VIN : input voltage, VOUT : output voltage, VDQ : input / output voltage These parameters are not 100% tested.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition Density of data hold Input leakage current A/DQ, DQ, /WAIT leakage current Operating supply current ICCA1 ILI ILO VIN = 0 V to VDDQ VDQ , VOUT = 0 V to VDDQ, /CE1 = VIH or /WE = VIL or /OE = VIH /CE1 = VIL, Burst length = 1, frequency = 83 MHz IDQ = 0 mA Operating supply Burst current Standby supply current ISB1 ICCA2 frequency = 66 MHz 60 55 40 35 128M bits T.B.D. mA mA -1.0 -1.0 +1.0 +1.0 MIN. TYP. MAX. Unit
A A
/CE1 = VIL, Burst length = 8, frequency = 83MHz IDQ = 0 mA /CE1 VDDQ-0.2 V, CE2 VDDQ-0.2 V frequency = 66MHz
A
ISB2
/CE1 VDDQ-0.2 V, CE2 0.2 V
64M bits 32M bits 16M bits 0M bit
T.B.D. T.B.D. T.B.D. T.B.D. 0.8VDDQ 0.2VDDQ V V
Output HIGH voltage Output LOW voltage
VOH VOL
IOH = -0.5 mA IOL = 1 mA
Remark VIN: Input voltage, VOUT: output voltage, VDQ: Input / Output voltage
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PD46128953-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 3 ns)
VDDQ 0.8VDDQ VDDQ / 2 0.2VDDQ VSSQ 3 ns Test points VDDQ / 2
Output Waveform
VDDQ / 2
Test Points
VDDQ / 2
Output Load 30 pF
Remark CL includes capacitance of the probe and jig, and stray capacitance.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
AC Specifications (1/2)
Parameter Symbol MIN. Clock Specifications Cycle frequency CLK HIGH width CLK LOW width CLK rise / fall time Address Latching Specifications Address hold time from /ADV = HIGH Address setup time to CLK Address hold time to CLK /ADV = LOW setup time to CLK /ADV = LOW hold time from CLK Address setup time to /OE = LOW /ADV = LOW pulse width /ADV = LOW to next /ADV = LOW Control Signals Specifications /CE1 setup time to CLK /CE1 hold time to CLK /OE setup time to CLK /OE hold time to CLK /WE setup time to CLK /WE hold time to CLK tCES tCEH tOES tOEH tWES tWEH 5 1 5 1 5 1 5 1 5 1 5 1 ns ns ns ns ns ns tAH tACS tACH tCSV tCHV tAOS tVPL tCVCV 1 5 7 5 1 0 6 10 1 5 7 5 1 0 6 10 ns ns ns ns ns ns ns tCLK tCH tCL tCHCL 3 3 3 83 3 3 3 66 MHz ns ns ns -E12X MAX. MIN. -E15X MAX. Unit Note
s
1
Note 1. tCVCV (MAX.) is applied while /CE1 is being hold at LOW.
Preliminary Data Sheet M17506EJ1V1DS
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PD46128953-X
(2/2)
Parameter Symbol MIN. Read Specifications Burst access time Output data hold CLK to output in high impedance Write Specifications Write data valid of CLK Write data hold of CLK DM setup time to CLK DM hold time to CLK /WAIT Specifications /WAIT LOW output time from CLK /WAIT HIGH output time from CLK /WAIT in high impedance from CLK Others /OE to output in low impedance Output time from /OE HIGH to LOW during burst read tOLZ tOAC 1 9 1 9 ns ns 2 1, 3, 4 tCEWA tCLWA tCWHZ 8 8 10 8 8 10 ns ns ns 1 1 2 tWDS tWDH tBDS tBDH 5 1 5 1 5 1 5 1 ns ns ns ns tAC tOH tHZ 2 7 8 2 7 8 ns ns ns 1, 3 1 2 -E12X MAX. MIN. -E15X MAX. Unit Note
Notes 1. 2. 3. 4.
Output load: 30 pF Output load: 5 pF In case output driver size is `Middle' For tOAC, refer to Figure 5-9. /OE HIGH to LOW during burst read operation timing.
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Preliminary Data Sheet M17506EJ1V1DS
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7. Timing Charts
Figure 7-1. Burst Read Cycle Timing Chart (/CE1 = LOW Consecutive Access)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tOEH tOES tOLZ tOEH tOES tAH tVPL tAH tCL tCVCV tCHCL tCHCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1
tOLZ tOEH tOES tOLZ
tOEH
tOES
tOEH tOES
/OE (Input)
tWES /WE (Input)
tWEH
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCEWA
Read Latency = 6 tAOS tAOS tAOS Add High-Z tHZ DQ22 to DQ31 (Output) High-Z Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 High-Z tAC tAC tOH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tACS A/DQ0 to A/DQ21 (Input/Output) High-Z
tACH
tHZ High-Z
tACS Add
tACH
tAOS High-Z
Remark The above timing chart assumes read latency is set 6.
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PD46128953-X
Figure 7-2. Burst Read Cycle Timing Chart (/CE1 Toggle Access)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tAH tVPL tCEH tCES tCEH tCES tCEH tCES tAH tCL tCVCV tCHCL tCHCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1
tOEH tOES /OE (Input)
tOLZ
tOEH
tOES
tOEH tOES
tWES /WE (Input)
tWEH
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCWHZ
tCEWA
tCLWA
Read Latency = 6 tAC High-Z tAC tOH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tACS A/DQ0 to A/DQ21 (Input/Output) High-Z Add
tACH
tAOS
tHZ High-Z
tACS Add
tACH
tAOS High-Z
tHZ DQ22 to DQ31 (Output) High-Z Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 High-Z
Remark The above timing chart assumes read latency is set 6.
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Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Figure 7-3. Burst Write Cycle Timing Chart (/CE1 = LOW Consecutive Access)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tAH tVPL tAH tCL tCVCV tCHCL tCHCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1
/OE (Input)
H
tWES /WE (Input)
tWEH
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCEWA
tBDS DM (Input)
tBDH
Write Latency = 5 tWDS tWDH D0 High-Z D1 D2 D3 D4 D5 D6 D7 High-Z
tACS A/DQ0 to A/DQ21 (Input) High-Z Add
tACH
tACS Add
tACH High-Z
DQ22 to DQ31 (Input)
High-Z
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
Remark The above timing chart assumes write latency is set 5.
Preliminary Data Sheet M17506EJ1V1DS
45
PD46128953-X
Figure 7-4. Burst Write Cycle Timing Chart (/CE1 Toggle Access)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tAH tVPL tCEH tCES tCEH tCES tCEH tCES tAH tCL tCVCV tCHCL tCHCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T0 T1
/OE (Input)
H
tWES /WE (Input)
tWEH
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCWHZ
tCEWA
tCLWA
tBDS DM (Input)
tBDH
Write Latency = 5 tWDS tWDH D0 High-Z D1 D2 D3 D4 D5 D6 D7 High-Z
tACS A/DQ0 to A/DQ21 (Input/Output) High-Z Add
tACH
tACS Add
tACH High-Z
DQ22 to DQ31 (Input)
High-Z
D0
D1
D2
D3
D4
D5
D6
D7
High-Z
Remark The above timing chart assumes write latency is set 5.
46
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 Controlled)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tAH tCEH tCES tCEH tVPL tCES tAH tCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T0 T1 T2 T3 T4 T5 T6 T7
tOEH tOES /OE (Input)
tOLZ
tOEH
tOES
tOEH tOES tOLZ
tWES tWEH /WE (Input)
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCWHZ High-Z
tCEWA
tCLWA
Read Latency = 6
Read Latency = 6 tAC tOH Q0 Q1 Q2
tACS A/DQ0 to A/DQ21 (Input/Output) High-Z Add
tACH
tAOS High-Z
tAC Q0
tHZ High-Z
tACS Add
tACH High-Z
tAOS
tAC
DQ22 to DQ31 (Output)
High-Z
Q0
High-Z
Q0
Q1
Q2
Note Burst Read Termination is available after the first read data output. Figure 7-5 is the minimum cycle at Burst Read Termination to next operation. Remark The above timing chart assumes read latency is set 6.
Preliminary Data Sheet M17506EJ1V1DS
47
PD46128953-X
Figure 7-6. Burst Write Termination Cycle Timing Chart (/CE1 Controlled)
T0 T1 T2 tCLK CLK (Input) tCH tCHV tCSV tCHV /ADV (Input) tVPL tCES /CE1 (Input) tAH tCEH tCES tCEH tVPL tCES tAH tCL tCHV tCSV tCHV T3 T4 T5 T6 T7 T0 T1 T2 T3 T4 T5 T6
/OE (Input)
H
tWES tWEH /WE (Input)
tWES tWEH
tCEWA /WAIT (Output) High-Z
tCLWA
tCWHZ High-Z
tCEWA
tCLWA
Write Latency = 5
Write Latency = 5
tACS A/DQ0 to A/DQ21 (Input) High-Z Add
tACH High-Z
tWDS tWDH D0 High-Z
tACS Add
tACH High-Z
tWDS tWDH D0 D1
DQ22 to DQ31 (Input)
High-Z
D0
High-Z
D0
D1
DM0 to DM3 (Input)
L
Note Burst Write Termination is available after the first write data input. Figure 7-6 is the minimum cycle at Burst Write Termination to next operation. Remark The above timing chart assumes write latency is set 5.
48
Preliminary Data Sheet M17506EJ1V1DS
8. 1 Mode Register Setting Timing
8. Mode Register Setting/Read Timing
Figure 8-1. Mode Register Setting Timing Chart
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
H CLK (Input) L
tVPL /ADV (Input)
tVPL
tVPL
tVPL
tVPL
tVPL
tCS tMSC /CE1 (Input)
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
Preliminary Data Sheet M17506EJ1V1DS
tCHZM
tOVL /OE (Input)
tWP
tWHP
tWP
tWHP
tWP
tWHP
tWP
tWHP
tWP
tWHP
/WE (Input)
tACM tOLZM tAOSM tAS tAH tOHZM
tAS
Don't Care
tAH
tDW
tDH
tAS
tAH
tDW
tDH
tAS
tAH
tDW
tDH
tAS
tAH
tDW
tDH
tAS
tAH
tDW
tDH
A/DQ0 to A/DQ21 (Input/Output)
Note
Note
Don't Care
Note
Don't Care
Note
Code1
Note
Code2
Note
Code3
DQ22 to DQ31 (Input/Output)
Don't Care
Don't Care
Don't Care
Code1
Code2
Code3
PD46128953-X
Note Address All "1" (3FFFFFH) Remark When setting the mode register, fix CLK to HIGH or LOW. If CLK is toggled, the mode register is not correctly set. When the mode register is set, DM0 to DM3 are don't care (HIGH or LOW). 49
PD46128953-X
8. 2 Mode Register Setting Flow Chart Figure 8-2. Mode Register Setting Flow Chart
Start
No
Read Operation Address = 3FFFFFH toggled the /CE1 and /OE Yes Write Operation Address = 3FFFFFH toggled the /CE1 Yes
No
No
Write Operation Address = 3FFFFFH toggled the /CE1 Yes Write Operation Address = 3FFFFFH toggled the /CE1 No
Mode register setting exit
Yes No
Write Data = Code1 Note 1 (A/DQ = 1) Yes Write Operation Address = 3FFFFFH toggled the /CE1 Yes
No
Write Data = Code2 Note 2
No
Yes Write Operation Address = 3FFFFFH toggled the /CE1 Yes No Write Data = Code3 Note 3 No
Yes End Re-setup the mode register
Notes 1. 2. 3.
Refer to Table 4-2. Refer to Table 4-3. Refer to Table 4-4.
50
Preliminary Data Sheet M17506EJ1V1DS
8. 3 Mode Register Read Timing
Figure 8-3. Mode Register Read Timing Chart
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
H
CLK (Input)
L
tVPL
/ADV (Input)
tVPL
tVPL
tVPL
tVPL
tVPL
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
tCS tMSC
tCP
Preliminary Data Sheet M17506EJ1V1DS
/CE1 (Input)
tCHZM
tOVL
/OE (Input)
tOVL
tOVL
tWP
tWHP
tWP
tWHP
tWP
/WE (Input)
tACM tOLZM tAOSM
tACM tOLZM
tACM tOLZM tAOSM
tDW tDH
tAS tAH
tOHZM
tAS
Don't Care
tAOSM
tAH
tDW tDH tAS tAH
tAS tAH
A/DQ0 to A/DQ21 (Input/Output) Note
tDW
tDH
tAS
tAH
tDW
tDH
tAS tAH
tDW
tDH
Note
Don't Care
Note
Don't Care
Note
Code1
Note
Code2
Note
Code3
DQ22 to DQ31 (Input/Output)
Don't Care
Don't Care
Don't Care
Code1
Code2
Code3
PD46128953-X
Note Address All "1" (3FFFFFH) Remark When setting the mode register, fix CLK to HIGH or LOW. If CLK is toggled, the mode register is not correctly set. When the mode register is set, DM0 to DM3 are don't care (HIGH or LOW).
51
PD46128953-X
8. 4 Mode Register Read Flow Chart Figure 8-4. Mode Register Read Flow Chart
Start
No
Read Operation Address = 3FFFFFH toggled the /CE1 and /OE Yes Write Operation Address = 3FFFFFH toggled the /CE1 Yes
No
No
Write Operation Address = 3FFFFFH toggled the /CE1 Yes Write Operation Address = 3FFFFFH toggled the /CE1 No
Mode register setting exit
Yes No
Write Data = Code1 Note 1 (A/DQ = 0) Yes Read Operation Address = 3FFFFFH toggled the /CE1 and /OE Yes
No
Read Data = Code2 Note 2
Read Operation Address = 3FFFFFH toggled the /CE1 and /OE Yes
No
Read Data = Code3 Note 3
End
Impossible Mode Register Read
Notes 1. 2. 3.
Refer to Table 4-2. Refer to Table 4-3. Refer to Table 4-4.
52
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
9. Standby Mode Timing Charts
Figure 9-1. Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits) Entry / Exit Timing Chart
CLK (Input)
tCE2S
CE2 (Input) tCES tCHML tMHCL1 tCES
/CE1 (Input) Standby mode 1 Standby mode 2 (Data hold: 64M bits / 32M bits / 16M bits)
Figure 9-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart
CLK (Input)
tCE2S
CE2 (Input) tCES tCHML tMHCL2 tCES
/CE1 (Input) Standby mode 1 Standby mode 2 (Data not held)
Standby Mode 2 Entry / Exit Timing
Parameter Standby mode 2 entry /CE1 HIGH to CE2 LOW Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW /CE1 setup time to CLK CE2 hold time to CLK Symbol tCHML tMHCL1 tMHCL2 tCES tCE2S MIN. 0 30 300 5 1 MAX. Unit ns ns 1 2 Note
s
ns ns
Notes 1. 2.
This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 64M bits / 32M bits / 16M bits). This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M17506EJ1V1DS
53
PD46128953-X
10. Package Drawing
The following is a package drawing of package sample.
127-PIN PLASTIC FBGA (13.0x11.5)
D WSA ZE ZD A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PNM L K J HG F E D C B A
B E
INDEX MARK
x4 v
WSB
A
y1
S
A2 S
ITEM D E v w e A A1 A2 b x y y1 ZD ZE (UNIT :mm) MILLIMETERS 13.00 11.50 0.15 0.20 0.80 1.50 0.22 1.28 0.40 0.08 0.10 0.20 1.30 0.55
y
S b
x
e
M
A1 S AB
This package drawing is a preliminary version. It may be changed in the future.
54
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
11. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD46128953-X. Type of Surface Mount Device
PD46128953F1-EB1: 127-pin PLASTIC FBGA (13.0 x 11.5)
Preliminary Data Sheet M17506EJ1V1DS
55
PD46128953-X
[ MEMO ]
56
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
[ MEMO ]
Preliminary Data Sheet M17506EJ1V1DS
57
PD46128953-X
[ MEMO ]
58
Preliminary Data Sheet M17506EJ1V1DS
PD46128953-X
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.
5
POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Preliminary Data Sheet M17506EJ1V1DS
59
PD46128953-X
* The information in this document is current as of September, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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